File Manager

X7ROOT File Manager

Current Path: /usr/include/linux

ðŸ“ ..
ðŸ“„ a.out.h(6.73 KB)
ðŸ“„ acct.h(3.65 KB)
ðŸ“„ adb.h(1.11 KB)
ðŸ“„ adfs_fs.h(936 B)
ðŸ“„ affs_hardblocks.h(1.51 KB)
ðŸ“„ agpgart.h(3.85 KB)
ðŸ“„ aio_abi.h(3.34 KB)
ðŸ“„ am437x-vpfe.h(3.59 KB)
ðŸ“ android
ðŸ“„ apm_bios.h(3.6 KB)
ðŸ“„ arcfb.h(213 B)
ðŸ“„ arm_sdei.h(2.69 KB)
ðŸ“„ aspeed-lpc-ctrl.h(1.74 KB)
ðŸ“„ atalk.h(1023 B)
ðŸ“„ atm.h(7.7 KB)
ðŸ“„ atm_eni.h(648 B)
ðŸ“„ atm_he.h(406 B)
ðŸ“„ atm_idt77105.h(955 B)
ðŸ“„ atm_nicstar.h(1.25 KB)
ðŸ“„ atm_tcp.h(1.58 KB)
ðŸ“„ atm_zatm.h(1.5 KB)
ðŸ“„ atmapi.h(952 B)
ðŸ“„ atmarp.h(1.27 KB)
ðŸ“„ atmbr2684.h(3.19 KB)
ðŸ“„ atmclip.h(576 B)
ðŸ“„ atmdev.h(7.5 KB)
ðŸ“„ atmioc.h(1.61 KB)
ðŸ“„ atmlec.h(2.33 KB)
ðŸ“„ atmmpc.h(4.13 KB)
ðŸ“„ atmppp.h(639 B)
ðŸ“„ atmsap.h(4.85 KB)
ðŸ“„ atmsvc.h(1.81 KB)
ðŸ“„ audit.h(19.92 KB)
ðŸ“„ auto_dev-ioctl.h(4.87 KB)
ðŸ“„ auto_fs.h(6.28 KB)
ðŸ“„ auto_fs4.h(451 B)
ðŸ“„ auxvec.h(1.56 KB)
ðŸ“„ ax25.h(2.76 KB)
ðŸ“„ b1lli.h(1.68 KB)
ðŸ“„ batadv_packet.h(20.01 KB)
ðŸ“„ batman_adv.h(11.7 KB)
ðŸ“„ baycom.h(883 B)
ðŸ“„ bcache.h(8.17 KB)
ðŸ“„ bcm933xx_hcs.h(419 B)
ðŸ“„ bfs_fs.h(1.85 KB)
ðŸ“„ binfmts.h(628 B)
ðŸ“„ blkpg.h(904 B)
ðŸ“„ blktrace_api.h(4.59 KB)
ðŸ“„ blkzoned.h(6.45 KB)
ðŸ“„ bpf.h(223.3 KB)
ðŸ“„ bpf_common.h(1.33 KB)
ðŸ“„ bpf_perf_event.h(529 B)
ðŸ“„ bpfilter.h(465 B)
ðŸ“„ bpqether.h(981 B)
ðŸ“„ bsg.h(2.44 KB)
ðŸ“„ bt-bmc.h(572 B)
ðŸ“„ btf.h(4.68 KB)
ðŸ“„ btrfs.h(28.24 KB)
ðŸ“„ btrfs_tree.h(24.69 KB)
ðŸ“ byteorder
ðŸ“ caif
ðŸ“ can
ðŸ“„ can.h(7.7 KB)
ðŸ“„ capability.h(13.2 KB)
ðŸ“„ capi.h(3.05 KB)
ðŸ“„ cciss_defs.h(3.2 KB)
ðŸ“„ cciss_ioctl.h(2.7 KB)
ðŸ“„ cdrom.h(28.18 KB)
ðŸ“„ cec-funcs.h(52.64 KB)
ðŸ“„ cec.h(36.81 KB)
ðŸ“„ cfm_bridge.h(1.42 KB)
ðŸ“„ cgroupstats.h(2.17 KB)
ðŸ“„ chio.h(5.22 KB)
ðŸ“ cifs
ðŸ“„ close_range.h(377 B)
ðŸ“„ cm4000_cs.h(1.76 KB)
ðŸ“„ cn_proc.h(3.38 KB)
ðŸ“„ coda.h(17.09 KB)
ðŸ“„ coda_psdev.h(783 B)
ðŸ“„ coff.h(12.18 KB)
ðŸ“„ connector.h(2.2 KB)
ðŸ“„ const.h(788 B)
ðŸ“„ coresight-stm.h(674 B)
ðŸ“„ cramfs_fs.h(3.47 KB)
ðŸ“„ cryptouser.h(3.31 KB)
ðŸ“„ cuda.h(905 B)
ðŸ“„ cyclades.h(16.71 KB)
ðŸ“„ cycx_cfm.h(2.92 KB)
ðŸ“„ dcbnl.h(24.65 KB)
ðŸ“„ dccp.h(6.29 KB)
ðŸ“„ devlink.h(21.05 KB)
ðŸ“„ dlm.h(2.49 KB)
ðŸ“„ dlm_device.h(2.48 KB)
ðŸ“„ dlm_netlink.h(1.13 KB)
ðŸ“„ dlm_plock.h(894 B)
ðŸ“„ dlmconstants.h(4.96 KB)
ðŸ“„ dm-ioctl.h(11.13 KB)
ðŸ“„ dm-log-userspace.h(14.83 KB)
ðŸ“„ dma-buf.h(5.12 KB)
ðŸ“„ dn.h(4.53 KB)
ðŸ“„ dqblk_xfs.h(9.03 KB)
ðŸ“ dvb
ðŸ“„ edd.h(5.47 KB)
ðŸ“„ efs_fs_sb.h(2.17 KB)
ðŸ“„ elf-em.h(2.14 KB)
ðŸ“„ elf-fdpic.h(1.1 KB)
ðŸ“„ elf.h(13.16 KB)
ðŸ“„ elfcore.h(2.92 KB)
ðŸ“„ errno.h(23 B)
ðŸ“„ errqueue.h(1.44 KB)
ðŸ“„ erspan.h(1.03 KB)
ðŸ“„ ethtool.h(81.89 KB)
ðŸ“„ ethtool_netlink.h(22.29 KB)
ðŸ“„ eventpoll.h(2.67 KB)
ðŸ“„ fadvise.h(842 B)
ðŸ“„ falloc.h(3.5 KB)
ðŸ“„ fanotify.h(5.22 KB)
ðŸ“„ fb.h(16.09 KB)
ðŸ“„ fcntl.h(4.08 KB)
ðŸ“„ fd.h(11.4 KB)
ðŸ“„ fdreg.h(5.29 KB)
ðŸ“„ fib_rules.h(1.99 KB)
ðŸ“„ fiemap.h(2.71 KB)
ðŸ“„ filter.h(2.16 KB)
ðŸ“„ firewire-cdev.h(42.86 KB)
ðŸ“„ firewire-constants.h(3.16 KB)
ðŸ“„ flat.h(2.1 KB)
ðŸ“„ fou.h(694 B)
ðŸ“„ fpga-dfl.h(8.52 KB)
ðŸ“„ fs.h(13.11 KB)
ðŸ“„ fsl_hypervisor.h(7.13 KB)
ðŸ“„ fsmap.h(4.29 KB)
ðŸ“„ fuse.h(22.92 KB)
ðŸ“„ futex.h(4.88 KB)
ðŸ“„ gameport.h(897 B)
ðŸ“„ gen_stats.h(1.49 KB)
ðŸ“„ genetlink.h(2.12 KB)
ðŸ“ genwqe
ðŸ“„ gfs2_ondisk.h(14.4 KB)
ðŸ“„ gigaset_dev.h(1.41 KB)
ðŸ“„ gpio.h(6.59 KB)
ðŸ“„ gsmmux.h(1.02 KB)
ðŸ“„ gtp.h(681 B)
ðŸ“„ hash_info.h(921 B)
ðŸ“ hdlc
ðŸ“„ hdlc.h(637 B)
ðŸ“„ hdlcdrv.h(2.84 KB)
ðŸ“„ hdreg.h(22.17 KB)
ðŸ“„ hid.h(1.86 KB)
ðŸ“„ hiddev.h(6.2 KB)
ðŸ“„ hidraw.h(1.95 KB)
ðŸ“„ hpet.h(743 B)
ðŸ“ hsi
ðŸ“„ hsr_netlink.h(1.06 KB)
ðŸ“„ hw_breakpoint.h(742 B)
ðŸ“„ hyperv.h(10.89 KB)
ðŸ“„ hysdn_if.h(1.35 KB)
ðŸ“„ i2c-dev.h(2.55 KB)
ðŸ“„ i2c.h(6.96 KB)
ðŸ“„ i2o-dev.h(11.28 KB)
ðŸ“„ i8k.h(1.49 KB)
ðŸ“„ icmp.h(2.91 KB)
ðŸ“„ icmpv6.h(3.94 KB)
ðŸ“„ idxd.h(8.22 KB)
ðŸ“„ if.h(10.65 KB)
ðŸ“„ if_addr.h(1.84 KB)
ðŸ“„ if_addrlabel.h(721 B)
ðŸ“„ if_alg.h(946 B)
ðŸ“„ if_arcnet.h(3.63 KB)
ðŸ“„ if_arp.h(6.42 KB)
ðŸ“„ if_bonding.h(5.17 KB)
ðŸ“„ if_bridge.h(19.06 KB)
ðŸ“„ if_cablemodem.h(986 B)
ðŸ“„ if_eql.h(1.32 KB)
ðŸ“„ if_ether.h(8.05 KB)
ðŸ“„ if_fc.h(1.7 KB)
ðŸ“„ if_fddi.h(3.66 KB)
ðŸ“„ if_frad.h(2.95 KB)
ðŸ“„ if_hippi.h(4.14 KB)
ðŸ“„ if_infiniband.h(1.22 KB)
ðŸ“„ if_link.h(30.28 KB)
ðŸ“„ if_ltalk.h(210 B)
ðŸ“„ if_macsec.h(5.7 KB)
ðŸ“„ if_packet.h(7.73 KB)
ðŸ“„ if_phonet.h(424 B)
ðŸ“„ if_plip.h(660 B)
ðŸ“„ if_ppp.h(29 B)
ðŸ“„ if_pppol2tp.h(3.21 KB)
ðŸ“„ if_pppox.h(4.76 KB)
ðŸ“„ if_slip.h(872 B)
ðŸ“„ if_team.h(2.54 KB)
ðŸ“„ if_tun.h(4 KB)
ðŸ“„ if_tunnel.h(4.41 KB)
ðŸ“„ if_vlan.h(1.79 KB)
ðŸ“„ if_x25.h(881 B)
ðŸ“„ if_xdp.h(2.94 KB)
ðŸ“„ ife.h(351 B)
ðŸ“„ igmp.h(2.99 KB)
ðŸ“ iio
ðŸ“„ ila.h(1.22 KB)
ðŸ“„ in.h(9.78 KB)
ðŸ“„ in6.h(7.26 KB)
ðŸ“„ in_route.h(936 B)
ðŸ“„ inet_diag.h(4.56 KB)
ðŸ“„ inotify.h(3.21 KB)
ðŸ“„ input-event-codes.h(27.94 KB)
ðŸ“„ input.h(15.61 KB)
ðŸ“„ io_uring.h(6.06 KB)
ðŸ“„ ioctl.h(163 B)
ðŸ“„ iommu.h(4.79 KB)
ðŸ“„ ip.h(4.62 KB)
ðŸ“„ ip6_tunnel.h(1.91 KB)
ðŸ“„ ip_vs.h(13.31 KB)
ðŸ“„ ipc.h(2.05 KB)
ðŸ“„ ipmi.h(15.08 KB)
ðŸ“„ ipmi_bmc.h(464 B)
ðŸ“„ ipmi_msgdefs.h(3.35 KB)
ðŸ“„ ipmi_ssif_bmc.h(441 B)
ðŸ“„ ipsec.h(947 B)
ðŸ“„ ipv6.h(3.87 KB)
ðŸ“„ ipv6_route.h(1.86 KB)
ðŸ“„ ipx.h(2.29 KB)
ðŸ“„ irqnr.h(104 B)
ðŸ“ isdn
ðŸ“„ isdn.h(5.64 KB)
ðŸ“„ isdn_divertif.h(1.17 KB)
ðŸ“„ isdn_ppp.h(1.88 KB)
ðŸ“„ isdnif.h(2.31 KB)
ðŸ“„ iso_fs.h(6.33 KB)
ðŸ“„ isst_if.h(5.26 KB)
ðŸ“„ ivtv.h(2.95 KB)
ðŸ“„ ivtvfb.h(1.18 KB)
ðŸ“„ jffs2.h(6.85 KB)
ðŸ“„ joystick.h(3.35 KB)
ðŸ“„ kcm.h(822 B)
ðŸ“„ kcmp.h(522 B)
ðŸ“„ kcov.h(1.07 KB)
ðŸ“„ kd.h(6.11 KB)
ðŸ“„ kdev_t.h(383 B)
ðŸ“„ kernel-page-flags.h(900 B)
ðŸ“„ kernel.h(438 B)
ðŸ“„ kernelcapi.h(1019 B)
ðŸ“„ kexec.h(1.79 KB)
ðŸ“„ keyboard.h(12.48 KB)
ðŸ“„ keyctl.h(3.42 KB)
ðŸ“„ kfd_ioctl.h(28.14 KB)
ðŸ“„ kfd_sysfs.h(4.25 KB)
ðŸ“„ kvm.h(60.12 KB)
ðŸ“„ kvm_para.h(1001 B)
ðŸ“„ l2tp.h(5.46 KB)
ðŸ“„ libc-compat.h(8.09 KB)
ðŸ“„ lightnvm.h(4.92 KB)
ðŸ“„ limits.h(937 B)
ðŸ“„ lirc.h(7.63 KB)
ðŸ“„ llc.h(3.09 KB)
ðŸ“„ loop.h(3.42 KB)
ðŸ“„ lp.h(4.09 KB)
ðŸ“„ lwtunnel.h(2.13 KB)
ðŸ“„ magic.h(3.45 KB)
ðŸ“„ major.h(4.6 KB)
ðŸ“„ map_to_7segment.h(7.08 KB)
ðŸ“„ matroxfb.h(1.43 KB)
ðŸ“„ max2175.h(1.01 KB)
ðŸ“„ mdio.h(16.87 KB)
ðŸ“„ media-bus-format.h(6.26 KB)
ðŸ“„ media.h(11.12 KB)
ðŸ“„ mei.h(3.39 KB)
ðŸ“„ membarrier.h(7.71 KB)
ðŸ“„ memfd.h(1.29 KB)
ðŸ“„ mempolicy.h(2.18 KB)
ðŸ“„ meye.h(2.47 KB)
ðŸ“„ mic_common.h(6.37 KB)
ðŸ“„ mic_ioctl.h(2.2 KB)
ðŸ“„ mii.h(9.27 KB)
ðŸ“„ minix_fs.h(2.07 KB)
ðŸ“„ mman.h(1.35 KB)
ðŸ“ mmc
ðŸ“„ mmtimer.h(2.07 KB)
ðŸ“„ module.h(255 B)
ðŸ“„ mount.h(4.44 KB)
ðŸ“„ mpls.h(2.25 KB)
ðŸ“„ mpls_iptunnel.h(761 B)
ðŸ“„ mptcp.h(5.48 KB)
ðŸ“„ mqueue.h(2.15 KB)
ðŸ“„ mroute.h(5.3 KB)
ðŸ“„ mroute6.h(4.47 KB)
ðŸ“„ mrp_bridge.h(1.67 KB)
ðŸ“„ msdos_fs.h(6.8 KB)
ðŸ“„ msg.h(3.29 KB)
ðŸ“„ mtio.h(7.98 KB)
ðŸ“„ n_r3964.h(2.35 KB)
ðŸ“„ nbd-netlink.h(2.35 KB)
ðŸ“„ nbd.h(2.95 KB)
ðŸ“„ ncsi.h(3.79 KB)
ðŸ“„ ndctl.h(6.71 KB)
ðŸ“„ neighbour.h(5.02 KB)
ðŸ“„ net.h(2.04 KB)
ðŸ“„ net_dropmon.h(2.85 KB)
ðŸ“„ net_namespace.h(715 B)
ðŸ“„ net_tstamp.h(5.67 KB)
ðŸ“„ netconf.h(614 B)
ðŸ“„ netdevice.h(2.2 KB)
ðŸ“ netfilter
ðŸ“„ netfilter.h(1.78 KB)
ðŸ“ netfilter_arp
ðŸ“„ netfilter_arp.h(445 B)
ðŸ“ netfilter_bridge
ðŸ“„ netfilter_bridge.h(1.14 KB)
ðŸ“„ netfilter_decnet.h(1.93 KB)
ðŸ“ netfilter_ipv4
ðŸ“„ netfilter_ipv4.h(2.12 KB)
ðŸ“ netfilter_ipv6
ðŸ“„ netfilter_ipv6.h(2.14 KB)
ðŸ“„ netlink.h(11.23 KB)
ðŸ“„ netlink_diag.h(1.49 KB)
ðŸ“„ netrom.h(807 B)
ðŸ“„ nexthop.h(1.5 KB)
ðŸ“„ nfc.h(10.95 KB)
ðŸ“„ nfs.h(4.39 KB)
ðŸ“„ nfs2.h(1.43 KB)
ðŸ“„ nfs3.h(2.4 KB)
ðŸ“„ nfs4.h(6.44 KB)
ðŸ“„ nfs4_mount.h(1.89 KB)
ðŸ“„ nfs_fs.h(1.6 KB)
ðŸ“„ nfs_idmap.h(2.19 KB)
ðŸ“„ nfs_mount.h(2.09 KB)
ðŸ“„ nfsacl.h(718 B)
ðŸ“ nfsd
ðŸ“„ nilfs2_api.h(7.41 KB)
ðŸ“„ nilfs2_ondisk.h(17.61 KB)
ðŸ“„ nitro_enclaves.h(12.84 KB)
ðŸ“„ nl80211.h(327.41 KB)
ðŸ“„ nsfs.h(639 B)
ðŸ“„ nubus.h(8 KB)
ðŸ“„ nvme_ioctl.h(2.06 KB)
ðŸ“„ nvram.h(532 B)
ðŸ“„ omap3isp.h(20.36 KB)
ðŸ“„ omapfb.h(5.78 KB)
ðŸ“„ oom.h(511 B)
ðŸ“„ openat2.h(1.26 KB)
ðŸ“„ openvswitch.h(39.24 KB)
ðŸ“„ packet_diag.h(1.63 KB)
ðŸ“„ param.h(141 B)
ðŸ“„ parport.h(3.56 KB)
ðŸ“„ patchkey.h(892 B)
ðŸ“„ pci.h(1.35 KB)
ðŸ“„ pci_regs.h(56.47 KB)
ðŸ“„ pcitest.h(711 B)
ðŸ“„ perf_event.h(39.63 KB)
ðŸ“„ personality.h(2.05 KB)
ðŸ“„ pfkeyv2.h(10.32 KB)
ðŸ“„ pfrut.h(7.8 KB)
ðŸ“„ pg.h(2.34 KB)
ðŸ“„ phantom.h(1.62 KB)
ðŸ“„ phonet.h(4.57 KB)
ðŸ“„ pkt_cls.h(18.08 KB)
ðŸ“„ pkt_sched.h(29.59 KB)
ðŸ“„ pktcdvd.h(2.62 KB)
ðŸ“„ pmu.h(5.19 KB)
ðŸ“„ poll.h(22 B)
ðŸ“„ posix_acl.h(1.22 KB)
ðŸ“„ posix_acl_xattr.h(1.09 KB)
ðŸ“„ posix_types.h(1.07 KB)
ðŸ“„ ppdev.h(3.14 KB)
ðŸ“„ ppp-comp.h(2.47 KB)
ðŸ“„ ppp-ioctl.h(5.35 KB)
ðŸ“„ ppp_defs.h(4.99 KB)
ðŸ“„ pps.h(4.62 KB)
ðŸ“„ pr.h(1.05 KB)
ðŸ“„ prctl.h(7.83 KB)
ðŸ“„ psample.h(2.22 KB)
ðŸ“„ psci.h(4.23 KB)
ðŸ“„ psp-sev.h(4.48 KB)
ðŸ“„ ptp_clock.h(7.28 KB)
ðŸ“„ ptrace.h(3.59 KB)
ðŸ“„ qemu_fw_cfg.h(2.41 KB)
ðŸ“„ qnx4_fs.h(2.27 KB)
ðŸ“„ qnxtypes.h(624 B)
ðŸ“„ qrtr.h(893 B)
ðŸ“„ quota.h(6.14 KB)
ðŸ“„ radeonfb.h(360 B)
ðŸ“ raid
ðŸ“„ random.h(1.34 KB)
ðŸ“„ raw.h(365 B)
ðŸ“„ rds.h(9.08 KB)
ðŸ“„ reboot.h(1.31 KB)
ðŸ“„ reiserfs_fs.h(775 B)
ðŸ“„ reiserfs_xattr.h(533 B)
ðŸ“„ resource.h(2.29 KB)
ðŸ“„ rfkill.h(6.45 KB)
ðŸ“„ rio_cm_cdev.h(3.17 KB)
ðŸ“„ rio_mport_cdev.h(9.11 KB)
ðŸ“„ romfs_fs.h(1.21 KB)
ðŸ“„ rose.h(2.18 KB)
ðŸ“„ route.h(2.28 KB)
ðŸ“„ rpmsg.h(544 B)
ðŸ“„ rseq.h(4.79 KB)
ðŸ“„ rtc.h(3.92 KB)
ðŸ“„ rtnetlink.h(19.73 KB)
ðŸ“„ rxrpc.h(4.96 KB)
ðŸ“„ scc.h(4.49 KB)
ðŸ“ sched
ðŸ“„ sched.h(2.73 KB)
ðŸ“„ scif_ioctl.h(6.23 KB)
ðŸ“„ screen_info.h(2.42 KB)
ðŸ“„ sctp.h(35.15 KB)
ðŸ“„ sdla.h(2.77 KB)
ðŸ“„ seccomp.h(2.2 KB)
ðŸ“„ securebits.h(2.64 KB)
ðŸ“„ sed-opal.h(3.2 KB)
ðŸ“„ seg6.h(1.14 KB)
ðŸ“„ seg6_genl.h(589 B)
ðŸ“„ seg6_hmac.h(423 B)
ðŸ“„ seg6_iptunnel.h(927 B)
ðŸ“„ seg6_local.h(2.01 KB)
ðŸ“„ selinux_netlink.h(1.17 KB)
ðŸ“„ sem.h(2.97 KB)
ðŸ“„ serial.h(3.78 KB)
ðŸ“„ serial_core.h(6.1 KB)
ðŸ“„ serial_reg.h(15.13 KB)
ðŸ“„ serio.h(1.99 KB)
ðŸ“„ sev-guest.h(2.25 KB)
ðŸ“„ shm.h(3.7 KB)
ðŸ“„ signal.h(388 B)
ðŸ“„ signalfd.h(1.2 KB)
ðŸ“„ smc.h(8.31 KB)
ðŸ“„ smc_diag.h(2.66 KB)
ðŸ“„ smiapp.h(1.03 KB)
ðŸ“„ snmp.h(13.34 KB)
ðŸ“„ sock_diag.h(1.27 KB)
ðŸ“„ socket.h(901 B)
ðŸ“„ sockios.h(5.96 KB)
ðŸ“„ sonet.h(2.24 KB)
ðŸ“„ sonypi.h(5.18 KB)
ðŸ“„ sound.h(1.21 KB)
ðŸ“„ soundcard.h(44.96 KB)
ðŸ“ spi
ðŸ“„ stat.h(6.2 KB)
ðŸ“„ stddef.h(1.5 KB)
ðŸ“„ stm.h(1.25 KB)
ðŸ“„ string.h(238 B)
ðŸ“ sunrpc
ðŸ“„ suspend_ioctls.h(1.4 KB)
ðŸ“„ swab.h(6.76 KB)
ðŸ“„ switchtec_ioctl.h(5.14 KB)
ðŸ“„ sync_file.h(2.82 KB)
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Editing: v4l2-dv-timings.h

/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
/*
 * V4L2 DV timings header.
 *
 * Copyright (C) 2012-2016  Hans Verkuil <hans.verkuil@cisco.com>
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * General Public License for more details.
 */

#ifndef _V4L2_DV_TIMINGS_H
#define _V4L2_DV_TIMINGS_H

#if __GNUC__ < 4 || (__GNUC__ == 4 && (__GNUC_MINOR__ < 6))
/* Sadly gcc versions older than 4.6 have a bug in how they initialize
   anonymous unions where they require additional curly brackets.
   This violates the C1x standard. This workaround adds the curly brackets
   if needed. */
#define V4L2_INIT_BT_TIMINGS(_width, args...) \
	{ .bt = { _width , ## args } }
#else
#define V4L2_INIT_BT_TIMINGS(_width, args...) \
	.bt = { _width , ## args }
#endif

/* CEA-861-F timings (i.e. standard HDTV timings) */

#define V4L2_DV_BT_CEA_640X480P59_94 { \
	.type = V4L2_DV_BT_656_1120, \
	V4L2_INIT_BT_TIMINGS(640, 480, 0, 0, \
		25175000, 16, 96, 48, 10, 2, 33, 0, 0, 0, \
		V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CEA861, \
		V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 1) \
}

/* Note: these are the nominal timings, for HDMI links this format is typically
 * double-clocked to meet the minimum pixelclock requirements.  */
#define V4L2_DV_BT_CEA_720X480I59_94 { \
	.type = V4L2_DV_BT_656_1120, \
	V4L2_INIT_BT_TIMINGS(720, 480, 1, 0, \
		13500000, 19, 62, 57, 4, 3, 15, 4, 3, 16, \
		V4L2_DV_BT_STD_CEA861, \
		V4L2_DV_FL_HALF_LINE | V4L2_DV_FL_IS_CE_VIDEO | \
		V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \
		{ 4, 3 }, 6) \
}

#define V4L2_DV_BT_CEA_720X480P59_94 { \
	.type = V4L2_DV_BT_656_1120, \
	V4L2_INIT_BT_TIMINGS(720, 480, 0, 0, \
		27000000, 16, 62, 60, 9, 6, 30, 0, 0, 0, \
		V4L2_DV_BT_STD_CEA861, \
		V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | \
		V4L2_DV_FL_HAS_CEA861_VIC, { 4, 3 }, 2) \
}

/* Note: these are the nominal timings, for HDMI links this format is typically
 * double-clocked to meet the minimum pixelclock requirements.  */
#define V4L2_DV_BT_CEA_720X576I50 { \
	.type = V4L2_DV_BT_656_1120, \
	V4L2_INIT_BT_TIMINGS(720, 576, 1, 0, \
		13500000, 12, 63, 69, 2, 3, 19, 2, 3, 20, \
		V4L2_DV_BT_STD_CEA861, \
		V4L2_DV_FL_HALF_LINE | V4L2_DV_FL_IS_CE_VIDEO | \
		V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \
		{ 4, 3 }, 21) \
}

#define V4L2_DV_BT_CEA_720X576P50 { \
	.type = V4L2_DV_BT_656_1120, \
	V4L2_INIT_BT_TIMINGS(720, 576, 0, 0, \
		27000000, 12, 64, 68, 5, 5, 39, 0, 0, 0, \
		V4L2_DV_BT_STD_CEA861, \
		V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | \
		V4L2_DV_FL_HAS_CEA861_VIC, { 4, 3 }, 17) \
}

#define V4L2_DV_BT_CEA_1280X720P24 { \
	.type = V4L2_DV_BT_656_1120, \
	V4L2_INIT_BT_TIMINGS(1280, 720, 0, \
		V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
		59400000, 1760, 40, 220, 5, 5, 20, 0, 0, 0, \
		V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CEA861, \
		V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 60) \
}

#define V4L2_DV_BT_CEA_1280X720P25 { \
	.type = V4L2_DV_BT_656_1120, \
	V4L2_INIT_BT_TIMINGS(1280, 720, 0, \
		V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
		74250000, 2420, 40, 220, 5, 5, 20, 0, 0, 0, \
		V4L2_DV_BT_STD_CEA861, \
		V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 61) \
}

#define V4L2_DV_BT_CEA_1280X720P30 { \
	.type = V4L2_DV_BT_656_1120, \
	V4L2_INIT_BT_TIMINGS(1280, 720, 0, \
		V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
		74250000, 1760, 40, 220, 5, 5, 20, 0, 0, 0, \
		V4L2_DV_BT_STD_CEA861, \
		V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
		V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 62) \
}

#define V4L2_DV_BT_CEA_1280X720P50 { \
	.type = V4L2_DV_BT_656_1120, \
	V4L2_INIT_BT_TIMINGS(1280, 720, 0, \
		V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
		74250000, 440, 40, 220, 5, 5, 20, 0, 0, 0, \
		V4L2_DV_BT_STD_CEA861, \
		V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 19) \
}

#define V4L2_DV_BT_CEA_1280X720P60 { \
	.type = V4L2_DV_BT_656_1120, \
	V4L2_INIT_BT_TIMINGS(1280, 720, 0, \
		V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
		74250000, 110, 40, 220, 5, 5, 20, 0, 0, 0, \
		V4L2_DV_BT_STD_CEA861, \
		V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
		V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 4) \
}

#define V4L2_DV_BT_CEA_1920X1080P24 { \
	.type = V4L2_DV_BT_656_1120, \
	V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \
		V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
		74250000, 638, 44, 148, 4, 5, 36, 0, 0, 0, \
		V4L2_DV_BT_STD_CEA861, \
		V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
		V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 32) \
}

#define V4L2_DV_BT_CEA_1920X1080P25 { \
	.type = V4L2_DV_BT_656_1120, \
	V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \
		V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
		74250000, 528, 44, 148, 4, 5, 36, 0, 0, 0, \
		V4L2_DV_BT_STD_CEA861, \
		V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 33) \
}

#define V4L2_DV_BT_CEA_1920X1080P30 { \
	.type = V4L2_DV_BT_656_1120, \
	V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \
		V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
		74250000, 88, 44, 148, 4, 5, 36, 0, 0, 0, \
		V4L2_DV_BT_STD_CEA861, \
		V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
		V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 34) \
}

#define V4L2_DV_BT_CEA_1920X1080I50 { \
	.type = V4L2_DV_BT_656_1120, \
	V4L2_INIT_BT_TIMINGS(1920, 1080, 1, \
		V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
		74250000, 528, 44, 148, 2, 5, 15, 2, 5, 16, \
		V4L2_DV_BT_STD_CEA861, \
		V4L2_DV_FL_HALF_LINE | V4L2_DV_FL_IS_CE_VIDEO | \
		V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 20) \
}

#define V4L2_DV_BT_CEA_1920X1080P50 { \
	.type = V4L2_DV_BT_656_1120, \
	V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \
		V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
		148500000, 528, 44, 148, 4, 5, 36, 0, 0, 0, \
		V4L2_DV_BT_STD_CEA861, \
		V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 31) \
}

#define V4L2_DV_BT_CEA_1920X1080I60 { \
	.type = V4L2_DV_BT_656_1120, \
	V4L2_INIT_BT_TIMINGS(1920, 1080, 1, \
		V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
		74250000, 88, 44, 148, 2, 5, 15, 2, 5, 16, \
		V4L2_DV_BT_STD_CEA861, \
		V4L2_DV_FL_CAN_REDUCE_FPS | \
		V4L2_DV_FL_HALF_LINE | V4L2_DV_FL_IS_CE_VIDEO | \
		V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 5) \
}

#define V4L2_DV_BT_CEA_1920X1080P60 { \
	.type = V4L2_DV_BT_656_1120, \
	V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \
		V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
		148500000, 88, 44, 148, 4, 5, 36, 0, 0, 0, \
		V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CEA861, \
		V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
		V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 16) \
}

#define V4L2_DV_BT_CEA_3840X2160P24 { \
	.type = V4L2_DV_BT_656_1120, \
	V4L2_INIT_BT_TIMINGS(3840, 2160, 0, \
		V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
		297000000, 1276, 88, 296, 8, 10, 72, 0, 0, 0, \
		V4L2_DV_BT_STD_CEA861, \
		V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
		V4L2_DV_FL_HAS_CEA861_VIC | V4L2_DV_FL_HAS_HDMI_VIC, \
		{ 0, 0 }, 93, 3) \
}

#define V4L2_DV_BT_CEA_3840X2160P25 { \
	.type = V4L2_DV_BT_656_1120, \
	V4L2_INIT_BT_TIMINGS(3840, 2160, 0, \
		V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
		297000000, 1056, 88, 296, 8, 10, 72, 0, 0, 0, \
		V4L2_DV_BT_STD_CEA861, \
		V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_CEA861_VIC | \
		V4L2_DV_FL_HAS_HDMI_VIC, { 0, 0 }, 94, 2) \
}

#define V4L2_DV_BT_CEA_3840X2160P30 { \
	.type = V4L2_DV_BT_656_1120, \
	V4L2_INIT_BT_TIMINGS(3840, 2160, 0, \
		V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
		297000000, 176, 88, 296, 8, 10, 72, 0, 0, 0, \
		V4L2_DV_BT_STD_CEA861, \
		V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
		V4L2_DV_FL_HAS_CEA861_VIC | V4L2_DV_FL_HAS_HDMI_VIC, \
		{ 0, 0 }, 95, 1) \
}

#define V4L2_DV_BT_CEA_3840X2160P50 { \
	.type = V4L2_DV_BT_656_1120, \
	V4L2_INIT_BT_TIMINGS(3840, 2160, 0, \
		V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
		594000000, 1056, 88, 296, 8, 10, 72, 0, 0, 0, \
		V4L2_DV_BT_STD_CEA861, \
		V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 96) \
}

#define V4L2_DV_BT_CEA_3840X2160P60 { \
	.type = V4L2_DV_BT_656_1120, \
	V4L2_INIT_BT_TIMINGS(3840, 2160, 0, \
		V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
		594000000, 176, 88, 296, 8, 10, 72, 0, 0, 0, \
		V4L2_DV_BT_STD_CEA861, \
		V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
		V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 97) \
}

#define V4L2_DV_BT_CEA_4096X2160P24 { \
	.type = V4L2_DV_BT_656_1120, \
	V4L2_INIT_BT_TIMINGS(4096, 2160, 0, \
		V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
		297000000, 1020, 88, 296, 8, 10, 72, 0, 0, 0, \
		V4L2_DV_BT_STD_CEA861, \
		V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
		V4L2_DV_FL_HAS_CEA861_VIC | V4L2_DV_FL_HAS_HDMI_VIC, \
		{ 0, 0 }, 98, 4) \
}

#define V4L2_DV_BT_CEA_4096X2160P25 { \
	.type = V4L2_DV_BT_656_1120, \
	V4L2_INIT_BT_TIMINGS(4096, 2160, 0, \
		V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
		297000000, 968, 88, 128, 8, 10, 72, 0, 0, 0, \
		V4L2_DV_BT_STD_CEA861, \
		V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 99) \
}

#define V4L2_DV_BT_CEA_4096X2160P30 { \
	.type = V4L2_DV_BT_656_1120, \
	V4L2_INIT_BT_TIMINGS(4096, 2160, 0, \
		V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
		297000000, 88, 88, 128, 8, 10, 72, 0, 0, 0, \
		V4L2_DV_BT_STD_CEA861, \
		V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
		V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 100) \
}

#define V4L2_DV_BT_CEA_4096X2160P50 { \
	.type = V4L2_DV_BT_656_1120, \
	V4L2_INIT_BT_TIMINGS(4096, 2160, 0, \
		V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
		594000000, 968, 88, 128, 8, 10, 72, 0, 0, 0, \
		V4L2_DV_BT_STD_CEA861, \
		V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 101) \
}

#define V4L2_DV_BT_CEA_4096X2160P60 { \
	.type = V4L2_DV_BT_656_1120, \
	V4L2_INIT_BT_TIMINGS(4096, 2160, 0, \
		V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
		594000000, 88, 88, 128, 8, 10, 72, 0, 0, 0, \
		V4L2_DV_BT_STD_CEA861, \
		V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
		V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 102) \
}

/* VESA Discrete Monitor Timings as per version 1.0, revision 12 */

#define V4L2_DV_BT_DMT_640X350P85 { \
	.type = V4L2_DV_BT_656_1120, \
	V4L2_INIT_BT_TIMINGS(640, 350, 0, V4L2_DV_HSYNC_POS_POL, \
		31500000, 32, 64, 96, 32, 3, 60, 0, 0, 0, \
		V4L2_DV_BT_STD_DMT, 0) \
}

#define V4L2_DV_BT_DMT_640X400P85 { \
	.type = V4L2_DV_BT_656_1120, \
	V4L2_INIT_BT_TIMINGS(640, 400, 0, V4L2_DV_VSYNC_POS_POL, \
		31500000, 32, 64, 96, 1, 3, 41, 0, 0, 0, \
		V4L2_DV_BT_STD_DMT, 0) \
}

#define V4L2_DV_BT_DMT_720X400P85 { \
	.type = V4L2_DV_BT_656_1120, \
	V4L2_INIT_BT_TIMINGS(720, 400, 0, V4L2_DV_VSYNC_POS_POL, \
		35500000, 36, 72, 108, 1, 3, 42, 0, 0, 0, \
		V4L2_DV_BT_STD_DMT, 0) \
}

/* VGA resolutions */
#define V4L2_DV_BT_DMT_640X480P60 V4L2_DV_BT_CEA_640X480P59_94

#define V4L2_DV_BT_DMT_640X480P72 { \
	.type = V4L2_DV_BT_656_1120, \
	V4L2_INIT_BT_TIMINGS(640, 480, 0, 0, \
		31500000, 24, 40, 128, 9, 3, 28, 0, 0, 0, \
		V4L2_DV_BT_STD_DMT, 0) \
}

#define V4L2_DV_BT_DMT_640X480P75 { \
	.type = V4L2_DV_BT_656_1120, \
	V4L2_INIT_BT_TIMINGS(640, 480, 0, 0, \
		31500000, 16, 64, 120, 1, 3, 16, 0, 0, 0, \
		V4L2_DV_BT_STD_DMT, 0) \
}

#define V4L2_DV_BT_DMT_640X480P85 { \
	.type = V4L2_DV_BT_656_1120, \
	V4L2_INIT_BT_TIMINGS(640, 480, 0, 0, \
		36000000, 56, 56, 80, 1, 3, 25, 0, 0, 0, \
		V4L2_DV_BT_STD_DMT, 0) \
}

/* SVGA resolutions */
#define V4L2_DV_BT_DMT_800X600P56 { \
	.type = V4L2_DV_BT_656_1120, \
	V4L2_INIT_BT_TIMINGS(800, 600, 0, \
		V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
		36000000, 24, 72, 128, 1, 2, 22, 0, 0, 0, \
		V4L2_DV_BT_STD_DMT, 0) \
}

#define V4L2_DV_BT_DMT_800X600P60 { \
	.type = V4L2_DV_BT_656_1120, \
	V4L2_INIT_BT_TIMINGS(800, 600, 0, \
		V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
		40000000, 40, 128, 88, 1, 4, 23, 0, 0, 0, \
		V4L2_DV_BT_STD_DMT, 0) \
}

#define V4L2_DV_BT_DMT_800X600P72 { \
	.type = V4L2_DV_BT_656_1120, \
	V4L2_INIT_BT_TIMINGS(800, 600, 0, \
		V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
		50000000, 56, 120, 64, 37, 6, 23, 0, 0, 0, \
		V4L2_DV_BT_STD_DMT, 0) \
}

#define V4L2_DV_BT_DMT_800X600P75 { \
	.type = V4L2_DV_BT_656_1120, \
	V4L2_INIT_BT_TIMINGS(800, 600, 0, \
		V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
		49500000, 16, 80, 160, 1, 3, 21, 0, 0, 0, \
		V4L2_DV_BT_STD_DMT, 0) \
}

#define V4L2_DV_BT_DMT_800X600P85 { \
	.type = V4L2_DV_BT_656_1120, \
	V4L2_INIT_BT_TIMINGS(800, 600, 0, \
		V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
		56250000, 32, 64, 152, 1, 3, 27, 0, 0, 0, \
		V4L2_DV_BT_STD_DMT, 0) \
}

#define V4L2_DV_BT_DMT_800X600P120_RB { \
	.type = V4L2_DV_BT_656_1120, \
	V4L2_INIT_BT_TIMINGS(800, 600, 0, V4L2_DV_HSYNC_POS_POL, \
		73250000, 48, 32, 80, 3, 4, 29, 0, 0, 0, \
		V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
		V4L2_DV_FL_REDUCED_BLANKING) \
}

#define V4L2_DV_BT_DMT_848X480P60 { \
	.type = V4L2_DV_BT_656_1120, \
	V4L2_INIT_BT_TIMINGS(848, 480, 0, \
		V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
		33750000, 16, 112, 112, 6, 8, 23, 0, 0, 0, \
		V4L2_DV_BT_STD_DMT, 0) \
}

#define V4L2_DV_BT_DMT_1024X768I43 { \
	.type = V4L2_DV_BT_656_1120, \
	V4L2_INIT_BT_TIMINGS(1024, 768, 1, \
		V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
		44900000, 8, 176, 56, 0, 4, 20, 0, 4, 21, \
		V4L2_DV_BT_STD_DMT, 0) \
}

/* XGA resolutions */
#define V4L2_DV_BT_DMT_1024X768P60 { \
	.type = V4L2_DV_BT_656_1120, \
	V4L2_INIT_BT_TIMINGS(1024, 768, 0, 0, \
		65000000, 24, 136, 160, 3, 6, 29, 0, 0, 0, \
		V4L2_DV_BT_STD_DMT, 0) \
}

#define V4L2_DV_BT_DMT_1024X768P70 { \
	.type = V4L2_DV_BT_656_1120, \
	V4L2_INIT_BT_TIMINGS(1024, 768, 0, 0, \
		75000000, 24, 136, 144, 3, 6, 29, 0, 0, 0, \
		V4L2_DV_BT_STD_DMT, 0) \
}

#define V4L2_DV_BT_DMT_1024X768P75 { \
	.type = V4L2_DV_BT_656_1120, \
	V4L2_INIT_BT_TIMINGS(1024, 768, 0, \
		V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
		78750000, 16, 96, 176, 1, 3, 28, 0, 0, 0, \
		V4L2_DV_BT_STD_DMT, 0) \
}

#define V4L2_DV_BT_DMT_1024X768P85 { \
	.type = V4L2_DV_BT_656_1120, \
	V4L2_INIT_BT_TIMINGS(1024, 768, 0, \
		V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
		94500000, 48, 96, 208, 1, 3, 36, 0, 0, 0, \
		V4L2_DV_BT_STD_DMT, 0) \
}

#define V4L2_DV_BT_DMT_1024X768P120_RB { \
	.type = V4L2_DV_BT_656_1120, \
	V4L2_INIT_BT_TIMINGS(1024, 768, 0, V4L2_DV_HSYNC_POS_POL, \
		115500000, 48, 32, 80, 3, 4, 38, 0, 0, 0, \
		V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
		V4L2_DV_FL_REDUCED_BLANKING) \
}

/* XGA+ resolution */
#define V4L2_DV_BT_DMT_1152X864P75 { \
	.type = V4L2_DV_BT_656_1120, \
	V4L2_INIT_BT_TIMINGS(1152, 864, 0, \
		V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
		108000000, 64, 128, 256, 1, 3, 32, 0, 0, 0, \
		V4L2_DV_BT_STD_DMT, 0) \
}

#define V4L2_DV_BT_DMT_1280X720P60 V4L2_DV_BT_CEA_1280X720P60

/* WXGA resolutions */
#define V4L2_DV_BT_DMT_1280X768P60_RB { \
	.type = V4L2_DV_BT_656_1120, \
	V4L2_INIT_BT_TIMINGS(1280, 768, 0, V4L2_DV_HSYNC_POS_POL, \
		68250000, 48, 32, 80, 3, 7, 12, 0, 0, 0, \
		V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
		V4L2_DV_FL_REDUCED_BLANKING) \
}

#define V4L2_DV_BT_DMT_1280X768P60 { \
	.type = V4L2_DV_BT_656_1120, \
	V4L2_INIT_BT_TIMINGS(1280, 768, 0, V4L2_DV_VSYNC_POS_POL, \
		79500000, 64, 128, 192, 3, 7, 20, 0, 0, 0, \
		V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
}

#define V4L2_DV_BT_DMT_1280X768P75 { \
	.type = V4L2_DV_BT_656_1120, \
	V4L2_INIT_BT_TIMINGS(1280, 768, 0, V4L2_DV_VSYNC_POS_POL, \
		102250000, 80, 128, 208, 3, 7, 27, 0, 0, 0, \
		V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
}

#define V4L2_DV_BT_DMT_1280X768P85 { \
	.type = V4L2_DV_BT_656_1120, \
	V4L2_INIT_BT_TIMINGS(1280, 768, 0, V4L2_DV_VSYNC_POS_POL, \
		117500000, 80, 136, 216, 3, 7, 31, 0, 0, 0, \
		V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
}

#define V4L2_DV_BT_DMT_1280X768P120_RB { \
	.type = V4L2_DV_BT_656_1120, \
	V4L2_INIT_BT_TIMINGS(1280, 768, 0, V4L2_DV_HSYNC_POS_POL, \
		140250000, 48, 32, 80, 3, 7, 35, 0, 0, 0, \
		V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
		V4L2_DV_FL_REDUCED_BLANKING) \
}

#define V4L2_DV_BT_DMT_1280X800P60_RB { \
	.type = V4L2_DV_BT_656_1120, \
	V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_HSYNC_POS_POL, \
		71000000, 48, 32, 80, 3, 6, 14, 0, 0, 0, \
		V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
		V4L2_DV_FL_REDUCED_BLANKING) \
}

#define V4L2_DV_BT_DMT_1280X800P60 { \
	.type = V4L2_DV_BT_656_1120, \
	V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_VSYNC_POS_POL, \
		83500000, 72, 128, 200, 3, 6, 22, 0, 0, 0, \
		V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
}

#define V4L2_DV_BT_DMT_1280X800P75 { \
	.type = V4L2_DV_BT_656_1120, \
	V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_VSYNC_POS_POL, \
		106500000, 80, 128, 208, 3, 6, 29, 0, 0, 0, \
		V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
}

#define V4L2_DV_BT_DMT_1280X800P85 { \
	.type = V4L2_DV_BT_656_1120, \
	V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_VSYNC_POS_POL, \
		122500000, 80, 136, 216, 3, 6, 34, 0, 0, 0, \
		V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
}

#define V4L2_DV_BT_DMT_1280X800P120_RB { \
	.type = V4L2_DV_BT_656_1120, \
	V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_HSYNC_POS_POL, \
		146250000, 48, 32, 80, 3, 6, 38, 0, 0, 0, \
		V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
		V4L2_DV_FL_REDUCED_BLANKING) \
}

#define V4L2_DV_BT_DMT_1280X960P60 { \
	.type = V4L2_DV_BT_656_1120, \
	V4L2_INIT_BT_TIMINGS(1280, 960, 0, \
		V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
		108000000, 96, 112, 312, 1, 3, 36, 0, 0, 0, \
		V4L2_DV_BT_STD_DMT, 0) \
}

#define V4L2_DV_BT_DMT_1280X960P85 { \
	.type = V4L2_DV_BT_656_1120, \
	V4L2_INIT_BT_TIMINGS(1280, 960, 0, \
		V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
		148500000, 64, 160, 224, 1, 3, 47, 0, 0, 0, \
		V4L2_DV_BT_STD_DMT, 0) \
}

#define V4L2_DV_BT_DMT_1280X960P120_RB { \
	.type = V4L2_DV_BT_656_1120, \
	V4L2_INIT_BT_TIMINGS(1280, 960, 0, V4L2_DV_HSYNC_POS_POL, \
		175500000, 48, 32, 80, 3, 4, 50, 0, 0, 0, \
		V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
		V4L2_DV_FL_REDUCED_BLANKING) \
}

/* SXGA resolutions */
#define V4L2_DV_BT_DMT_1280X1024P60 { \
	.type = V4L2_DV_BT_656_1120, \
	V4L2_INIT_BT_TIMINGS(1280, 1024, 0, \
		V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
		108000000, 48, 112, 248, 1, 3, 38, 0, 0, 0, \
		V4L2_DV_BT_STD_DMT, 0) \
}

#define V4L2_DV_BT_DMT_1280X1024P75 { \
	.type = V4L2_DV_BT_656_1120, \
	V4L2_INIT_BT_TIMINGS(1280, 1024, 0, \
		V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
		135000000, 16, 144, 248, 1, 3, 38, 0, 0, 0, \
		V4L2_DV_BT_STD_DMT, 0) \
}

#define V4L2_DV_BT_DMT_1280X1024P85 { \
	.type = V4L2_DV_BT_656_1120, \
	V4L2_INIT_BT_TIMINGS(1280, 1024, 0, \
		V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
		157500000, 64, 160, 224, 1, 3, 44, 0, 0, 0, \
		V4L2_DV_BT_STD_DMT, 0) \
}

#define V4L2_DV_BT_DMT_1280X1024P120_RB { \
	.type = V4L2_DV_BT_656_1120, \
	V4L2_INIT_BT_TIMINGS(1280, 1024, 0, V4L2_DV_HSYNC_POS_POL, \
		187250000, 48, 32, 80, 3, 7, 50, 0, 0, 0, \
		V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
		V4L2_DV_FL_REDUCED_BLANKING) \
}

#define V4L2_DV_BT_DMT_1360X768P60 { \
	.type = V4L2_DV_BT_656_1120, \
	V4L2_INIT_BT_TIMINGS(1360, 768, 0, \
		V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
		85500000, 64, 112, 256, 3, 6, 18, 0, 0, 0, \
		V4L2_DV_BT_STD_DMT, 0) \
}

#define V4L2_DV_BT_DMT_1360X768P120_RB { \
	.type = V4L2_DV_BT_656_1120, \
	V4L2_INIT_BT_TIMINGS(1360, 768, 0, V4L2_DV_HSYNC_POS_POL, \
		148250000, 48, 32, 80, 3, 5, 37, 0, 0, 0, \
		V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
		V4L2_DV_FL_REDUCED_BLANKING) \
}

#define V4L2_DV_BT_DMT_1366X768P60 { \
	.type = V4L2_DV_BT_656_1120, \
	V4L2_INIT_BT_TIMINGS(1366, 768, 0, \
		V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
		85500000, 70, 143, 213, 3, 3, 24, 0, 0, 0, \
		V4L2_DV_BT_STD_DMT, 0) \
}

#define V4L2_DV_BT_DMT_1366X768P60_RB { \
	.type = V4L2_DV_BT_656_1120, \
	V4L2_INIT_BT_TIMINGS(1366, 768, 0, \
		V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
		72000000, 14, 56, 64, 1, 3, 28, 0, 0, 0, \
		V4L2_DV_BT_STD_DMT, V4L2_DV_FL_REDUCED_BLANKING) \
}

/* SXGA+ resolutions */
#define V4L2_DV_BT_DMT_1400X1050P60_RB { \
	.type = V4L2_DV_BT_656_1120, \
	V4L2_INIT_BT_TIMINGS(1400, 1050, 0, V4L2_DV_HSYNC_POS_POL, \
		101000000, 48, 32, 80, 3, 4, 23, 0, 0, 0, \
		V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
		V4L2_DV_FL_REDUCED_BLANKING) \
}

#define V4L2_DV_BT_DMT_1400X1050P60 { \
	.type = V4L2_DV_BT_656_1120, \
	V4L2_INIT_BT_TIMINGS(1400, 1050, 0, V4L2_DV_VSYNC_POS_POL, \
		121750000, 88, 144, 232, 3, 4, 32, 0, 0, 0, \
		V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
}

#define V4L2_DV_BT_DMT_1400X1050P75 { \
	.type = V4L2_DV_BT_656_1120, \
	V4L2_INIT_BT_TIMINGS(1400, 1050, 0, V4L2_DV_VSYNC_POS_POL, \
		156000000, 104, 144, 248, 3, 4, 42, 0, 0, 0, \
		V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
}

#define V4L2_DV_BT_DMT_1400X1050P85 { \
	.type = V4L2_DV_BT_656_1120, \
	V4L2_INIT_BT_TIMINGS(1400, 1050, 0, V4L2_DV_VSYNC_POS_POL, \
		179500000, 104, 152, 256, 3, 4, 48, 0, 0, 0, \
		V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
}

#define V4L2_DV_BT_DMT_1400X1050P120_RB { \
	.type = V4L2_DV_BT_656_1120, \
	V4L2_INIT_BT_TIMINGS(1400, 1050, 0, V4L2_DV_HSYNC_POS_POL, \
		208000000, 48, 32, 80, 3, 4, 55, 0, 0, 0, \
		V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
		V4L2_DV_FL_REDUCED_BLANKING) \
}

/* WXGA+ resolutions */
#define V4L2_DV_BT_DMT_1440X900P60_RB { \
	.type = V4L2_DV_BT_656_1120, \
	V4L2_INIT_BT_TIMINGS(1440, 900, 0, V4L2_DV_HSYNC_POS_POL, \
		88750000, 48, 32, 80, 3, 6, 17, 0, 0, 0, \
		V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
		V4L2_DV_FL_REDUCED_BLANKING) \
}

#define V4L2_DV_BT_DMT_1440X900P60 { \
	.type = V4L2_DV_BT_656_1120, \
	V4L2_INIT_BT_TIMINGS(1440, 900, 0, V4L2_DV_VSYNC_POS_POL, \
		106500000, 80, 152, 232, 3, 6, 25, 0, 0, 0, \
		V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
}

#define V4L2_DV_BT_DMT_1440X900P75 { \
	.type = V4L2_DV_BT_656_1120, \
	V4L2_INIT_BT_TIMINGS(1440, 900, 0, V4L2_DV_VSYNC_POS_POL, \
		136750000, 96, 152, 248, 3, 6, 33, 0, 0, 0, \
		V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
}

#define V4L2_DV_BT_DMT_1440X900P85 { \
	.type = V4L2_DV_BT_656_1120, \
	V4L2_INIT_BT_TIMINGS(1440, 900, 0, V4L2_DV_VSYNC_POS_POL, \
		157000000, 104, 152, 256, 3, 6, 39, 0, 0, 0, \
		V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
}

#define V4L2_DV_BT_DMT_1440X900P120_RB { \
	.type = V4L2_DV_BT_656_1120, \
	V4L2_INIT_BT_TIMINGS(1440, 900, 0, V4L2_DV_HSYNC_POS_POL, \
		182750000, 48, 32, 80, 3, 6, 44, 0, 0, 0, \
		V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
		V4L2_DV_FL_REDUCED_BLANKING) \
}

#define V4L2_DV_BT_DMT_1600X900P60_RB { \
	.type = V4L2_DV_BT_656_1120, \
	V4L2_INIT_BT_TIMINGS(1600, 900, 0, \
		V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
		108000000, 24, 80, 96, 1, 3, 96, 0, 0, 0, \
		V4L2_DV_BT_STD_DMT, V4L2_DV_FL_REDUCED_BLANKING) \
}

/* UXGA resolutions */
#define V4L2_DV_BT_DMT_1600X1200P60 { \
	.type = V4L2_DV_BT_656_1120, \
	V4L2_INIT_BT_TIMINGS(1600, 1200, 0, \
		V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
		162000000, 64, 192, 304, 1, 3, 46, 0, 0, 0, \
		V4L2_DV_BT_STD_DMT, 0) \
}

#define V4L2_DV_BT_DMT_1600X1200P65 { \
	.type = V4L2_DV_BT_656_1120, \
	V4L2_INIT_BT_TIMINGS(1600, 1200, 0, \
		V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
		175500000, 64, 192, 304, 1, 3, 46, 0, 0, 0, \
		V4L2_DV_BT_STD_DMT, 0) \
}

#define V4L2_DV_BT_DMT_1600X1200P70 { \
	.type = V4L2_DV_BT_656_1120, \
	V4L2_INIT_BT_TIMINGS(1600, 1200, 0, \
		V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
		189000000, 64, 192, 304, 1, 3, 46, 0, 0, 0, \
		V4L2_DV_BT_STD_DMT, 0) \
}

#define V4L2_DV_BT_DMT_1600X1200P75 { \
	.type = V4L2_DV_BT_656_1120, \
	V4L2_INIT_BT_TIMINGS(1600, 1200, 0, \
		V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
		202500000, 64, 192, 304, 1, 3, 46, 0, 0, 0, \
		V4L2_DV_BT_STD_DMT, 0) \
}

#define V4L2_DV_BT_DMT_1600X1200P85 { \
	.type = V4L2_DV_BT_656_1120, \
	V4L2_INIT_BT_TIMINGS(1600, 1200, 0, \
		V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
		229500000, 64, 192, 304, 1, 3, 46, 0, 0, 0, \
		V4L2_DV_BT_STD_DMT, 0) \
}

#define V4L2_DV_BT_DMT_1600X1200P120_RB { \
	.type = V4L2_DV_BT_656_1120, \
	V4L2_INIT_BT_TIMINGS(1600, 1200, 0, V4L2_DV_HSYNC_POS_POL, \
		268250000, 48, 32, 80, 3, 4, 64, 0, 0, 0, \
		V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
		V4L2_DV_FL_REDUCED_BLANKING) \
}

/* WSXGA+ resolutions */
#define V4L2_DV_BT_DMT_1680X1050P60_RB { \
	.type = V4L2_DV_BT_656_1120, \
	V4L2_INIT_BT_TIMINGS(1680, 1050, 0, V4L2_DV_HSYNC_POS_POL, \
		119000000, 48, 32, 80, 3, 6, 21, 0, 0, 0, \
		V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
		V4L2_DV_FL_REDUCED_BLANKING) \
}

#define V4L2_DV_BT_DMT_1680X1050P60 { \
	.type = V4L2_DV_BT_656_1120, \
	V4L2_INIT_BT_TIMINGS(1680, 1050, 0, V4L2_DV_VSYNC_POS_POL, \
		146250000, 104, 176, 280, 3, 6, 30, 0, 0, 0, \
		V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
}

#define V4L2_DV_BT_DMT_1680X1050P75 { \
	.type = V4L2_DV_BT_656_1120, \
	V4L2_INIT_BT_TIMINGS(1680, 1050, 0, V4L2_DV_VSYNC_POS_POL, \
		187000000, 120, 176, 296, 3, 6, 40, 0, 0, 0, \
		V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
}

#define V4L2_DV_BT_DMT_1680X1050P85 { \
	.type = V4L2_DV_BT_656_1120, \
	V4L2_INIT_BT_TIMINGS(1680, 1050, 0, V4L2_DV_VSYNC_POS_POL, \
		214750000, 128, 176, 304, 3, 6, 46, 0, 0, 0, \
		V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
}

#define V4L2_DV_BT_DMT_1680X1050P120_RB { \
	.type = V4L2_DV_BT_656_1120, \
	V4L2_INIT_BT_TIMINGS(1680, 1050, 0, V4L2_DV_HSYNC_POS_POL, \
		245500000, 48, 32, 80, 3, 6, 53, 0, 0, 0, \
		V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
		V4L2_DV_FL_REDUCED_BLANKING) \
}

#define V4L2_DV_BT_DMT_1792X1344P60 { \
	.type = V4L2_DV_BT_656_1120, \
	V4L2_INIT_BT_TIMINGS(1792, 1344, 0, V4L2_DV_VSYNC_POS_POL, \
		204750000, 128, 200, 328, 1, 3, 46, 0, 0, 0, \
		V4L2_DV_BT_STD_DMT, 0) \
}

#define V4L2_DV_BT_DMT_1792X1344P75 { \
	.type = V4L2_DV_BT_656_1120, \
	V4L2_INIT_BT_TIMINGS(1792, 1344, 0, V4L2_DV_VSYNC_POS_POL, \
		261000000, 96, 216, 352, 1, 3, 69, 0, 0, 0, \
		V4L2_DV_BT_STD_DMT, 0) \
}

#define V4L2_DV_BT_DMT_1792X1344P120_RB { \
	.type = V4L2_DV_BT_656_1120, \
	V4L2_INIT_BT_TIMINGS(1792, 1344, 0, V4L2_DV_HSYNC_POS_POL, \
		333250000, 48, 32, 80, 3, 4, 72, 0, 0, 0, \
		V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
		V4L2_DV_FL_REDUCED_BLANKING) \
}

#define V4L2_DV_BT_DMT_1856X1392P60 { \
	.type = V4L2_DV_BT_656_1120, \
	V4L2_INIT_BT_TIMINGS(1856, 1392, 0, V4L2_DV_VSYNC_POS_POL, \
		218250000, 96, 224, 352, 1, 3, 43, 0, 0, 0, \
		V4L2_DV_BT_STD_DMT, 0) \
}

#define V4L2_DV_BT_DMT_1856X1392P75 { \
	.type = V4L2_DV_BT_656_1120, \
	V4L2_INIT_BT_TIMINGS(1856, 1392, 0, V4L2_DV_VSYNC_POS_POL, \
		288000000, 128, 224, 352, 1, 3, 104, 0, 0, 0, \
		V4L2_DV_BT_STD_DMT, 0) \
}

#define V4L2_DV_BT_DMT_1856X1392P120_RB { \
	.type = V4L2_DV_BT_656_1120, \
	V4L2_INIT_BT_TIMINGS(1856, 1392, 0, V4L2_DV_HSYNC_POS_POL, \
		356500000, 48, 32, 80, 3, 4, 75, 0, 0, 0, \
		V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
		V4L2_DV_FL_REDUCED_BLANKING) \
}

#define V4L2_DV_BT_DMT_1920X1080P60 V4L2_DV_BT_CEA_1920X1080P60

/* WUXGA resolutions */
#define V4L2_DV_BT_DMT_1920X1200P60_RB { \
	.type = V4L2_DV_BT_656_1120, \
	V4L2_INIT_BT_TIMINGS(1920, 1200, 0, V4L2_DV_HSYNC_POS_POL, \
		154000000, 48, 32, 80, 3, 6, 26, 0, 0, 0, \
		V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
		V4L2_DV_FL_REDUCED_BLANKING) \
}

#define V4L2_DV_BT_DMT_1920X1200P60 { \
	.type = V4L2_DV_BT_656_1120, \
	V4L2_INIT_BT_TIMINGS(1920, 1200, 0, V4L2_DV_VSYNC_POS_POL, \
		193250000, 136, 200, 336, 3, 6, 36, 0, 0, 0, \
		V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
}

#define V4L2_DV_BT_DMT_1920X1200P75 { \
	.type = V4L2_DV_BT_656_1120, \
	V4L2_INIT_BT_TIMINGS(1920, 1200, 0, V4L2_DV_VSYNC_POS_POL, \
		245250000, 136, 208, 344, 3, 6, 46, 0, 0, 0, \
		V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
}

#define V4L2_DV_BT_DMT_1920X1200P85 { \
	.type = V4L2_DV_BT_656_1120, \
	V4L2_INIT_BT_TIMINGS(1920, 1200, 0, V4L2_DV_VSYNC_POS_POL, \
		281250000, 144, 208, 352, 3, 6, 53, 0, 0, 0, \
		V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
}

#define V4L2_DV_BT_DMT_1920X1200P120_RB { \
	.type = V4L2_DV_BT_656_1120, \
	V4L2_INIT_BT_TIMINGS(1920, 1200, 0, V4L2_DV_HSYNC_POS_POL, \
		317000000, 48, 32, 80, 3, 6, 62, 0, 0, 0, \
		V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
		V4L2_DV_FL_REDUCED_BLANKING) \
}

#define V4L2_DV_BT_DMT_1920X1440P60 { \
	.type = V4L2_DV_BT_656_1120, \
	V4L2_INIT_BT_TIMINGS(1920, 1440, 0, V4L2_DV_VSYNC_POS_POL, \
		234000000, 128, 208, 344, 1, 3, 56, 0, 0, 0, \
		V4L2_DV_BT_STD_DMT, 0) \
}

#define V4L2_DV_BT_DMT_1920X1440P75 { \
	.type = V4L2_DV_BT_656_1120, \
	V4L2_INIT_BT_TIMINGS(1920, 1440, 0, V4L2_DV_VSYNC_POS_POL, \
		297000000, 144, 224, 352, 1, 3, 56, 0, 0, 0, \
		V4L2_DV_BT_STD_DMT, 0) \
}

#define V4L2_DV_BT_DMT_1920X1440P120_RB { \
	.type = V4L2_DV_BT_656_1120, \
	V4L2_INIT_BT_TIMINGS(1920, 1440, 0, V4L2_DV_HSYNC_POS_POL, \
		380500000, 48, 32, 80, 3, 4, 78, 0, 0, 0, \
		V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
		V4L2_DV_FL_REDUCED_BLANKING) \
}

#define V4L2_DV_BT_DMT_2048X1152P60_RB { \
	.type = V4L2_DV_BT_656_1120, \
	V4L2_INIT_BT_TIMINGS(2048, 1152, 0, \
		V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
		162000000, 26, 80, 96, 1, 3, 44, 0, 0, 0, \
		V4L2_DV_BT_STD_DMT, V4L2_DV_FL_REDUCED_BLANKING) \
}

/* WQXGA resolutions */
#define V4L2_DV_BT_DMT_2560X1600P60_RB { \
	.type = V4L2_DV_BT_656_1120, \
	V4L2_INIT_BT_TIMINGS(2560, 1600, 0, V4L2_DV_HSYNC_POS_POL, \
		268500000, 48, 32, 80, 3, 6, 37, 0, 0, 0, \
		V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
		V4L2_DV_FL_REDUCED_BLANKING) \
}

#define V4L2_DV_BT_DMT_2560X1600P60 { \
	.type = V4L2_DV_BT_656_1120, \
	V4L2_INIT_BT_TIMINGS(2560, 1600, 0, V4L2_DV_VSYNC_POS_POL, \
		348500000, 192, 280, 472, 3, 6, 49, 0, 0, 0, \
		V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
}

#define V4L2_DV_BT_DMT_2560X1600P75 { \
	.type = V4L2_DV_BT_656_1120, \
	V4L2_INIT_BT_TIMINGS(2560, 1600, 0, V4L2_DV_VSYNC_POS_POL, \
		443250000, 208, 280, 488, 3, 6, 63, 0, 0, 0, \
		V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
}

#define V4L2_DV_BT_DMT_2560X1600P85 { \
	.type = V4L2_DV_BT_656_1120, \
	V4L2_INIT_BT_TIMINGS(2560, 1600, 0, V4L2_DV_VSYNC_POS_POL, \
		505250000, 208, 280, 488, 3, 6, 73, 0, 0, 0, \
		V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
}

#define V4L2_DV_BT_DMT_2560X1600P120_RB { \
	.type = V4L2_DV_BT_656_1120, \
	V4L2_INIT_BT_TIMINGS(2560, 1600, 0, V4L2_DV_HSYNC_POS_POL, \
		552750000, 48, 32, 80, 3, 6, 85, 0, 0, 0, \
		V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
		V4L2_DV_FL_REDUCED_BLANKING) \
}

/* 4K resolutions */
#define V4L2_DV_BT_DMT_4096X2160P60_RB { \
	.type = V4L2_DV_BT_656_1120, \
	V4L2_INIT_BT_TIMINGS(4096, 2160, 0, V4L2_DV_HSYNC_POS_POL, \
		556744000, 8, 32, 40, 48, 8, 6, 0, 0, 0, \
		V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
		V4L2_DV_FL_REDUCED_BLANKING) \
}

#define V4L2_DV_BT_DMT_4096X2160P59_94_RB { \
	.type = V4L2_DV_BT_656_1120, \
	V4L2_INIT_BT_TIMINGS(4096, 2160, 0, V4L2_DV_HSYNC_POS_POL, \
		556188000, 8, 32, 40, 48, 8, 6, 0, 0, 0, \
		V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
		V4L2_DV_FL_REDUCED_BLANKING) \
}

/* SDI timings definitions */

/* SMPTE-125M */
#define V4L2_DV_BT_SDI_720X487I60 { \
	.type = V4L2_DV_BT_656_1120, \
	V4L2_INIT_BT_TIMINGS(720, 487, 1, \
		V4L2_DV_HSYNC_POS_POL, \
		13500000, 16, 121, 0, 0, 19, 0, 0, 19, 0, \
		V4L2_DV_BT_STD_SDI, \
		V4L2_DV_FL_FIRST_FIELD_EXTRA_LINE) \
}

#endif

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